With continuous development of fabrication technology of integrated circuits (ICs), the requirements on the integration degree and the performance of ICs become higher and higher. In order to improve the integration degree, the critical dimensions of semiconductor devices continuously decrease and the distances between neighboring devices also become smaller and smaller, increasing technological requirements on IC fabrication.
In order to reduce the parasitic capacitance of gate electrodes and improve operation speed of semiconductor devices, a high-k metal gate (HKMG) structure, including a high-k gate dielectric layer and a metal gate electrode, has been adapted in semiconductor devices. To further reduce negative influence of the material used for the metal gate electrode on other structures in the semiconductor device, the bi-layer structure of HKMG, including a metal gate electrode and a high-k gate dielectric layer, is usually fabricated by a gate last process.
For example, forming a HKMG structure through a gate last process may include the following steps. First, a substrate may be provided. The substrate may include a dielectric layer formed on the substrate and a plurality of dummy gate structures formed in the dielectric layer. Then, a plurality of openings may be formed on the substrate by removing the plurality of dummy gate structures. The bottom of each opening may expose a portion of the surface of the substrate. Further, a gate dielectric layer may be formed on the exposed surface of the substrate in each opening and a metal gate electrode may then be formed on the gate dielectric layer. Specifically, the gate dielectric layer may be made of a material including a high-k dielectric material.
As the dimension of a device becomes smaller, the size of the gate electrode in the semiconductor structure may also decrease. Therefore, during the fabrication process, filling a conductive material into an opening with a decreased lateral dimension becomes more difficult, and thus the quality of the formed gate structure may be affected and the performance of the formed semiconductor structure may be degraded. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.